1. Field of the Invention
The present invention relates to a computer-controlled automatic logic design system for semiconductor integrated circuit devices and, more particularly, to a design automation tool for designing, based on a "hardware description language", a desired custom logic function which uses logic elements selected from standard logic elements which are known as "standard cells" and stored in advance as a library.
2. Description of the Related Art
As the size of semiconductor components such as ICs and LSIs is increased, digital computers are recently used to automatically design their internal logic circuits, thereby increasing the design efficiency. In automatic design of the internal logic circuits of LSIs, the operator or designer describes and designates the desired function or operation of the internal logic circuits by using a special computer language called "hardware description language". In an automatic logic design system, circuit elements required for real&zing the desired logic function described by the "hardware description language" are selected from standard cells stored in advance as a library and are synthesized, thereby constituting a circuit pattern that performs the designated logic operation.
Generally, a circuit which is automatically designed in the above manner cannot be directly applied to practical LSI patterns: this is due to the fact that, in the actual LSI chips, it is required that the element layout on a chip substrate must be rearranged such that (1) the layout restrictions and wiring conditions of the logic elements must be satisfied as much as possible, and (2) the entire area of the chip is minimized as much as possible by minimizing extra wiring spaces among the elements. The automatic logic design based on the "hardware description language" described above is basically directed only to automatic synthesis of the circuit for realizing a desired function, and the element layout conditions and wiring rules of an actual LSI chip are not considered. The automatic logic design system has an automatic layout processing unit, which cannot effectively obtain an optimal layout of a circuit pattern, since a currently available automatic layout algorithm is not so strong as to rearrange the constituted complex entire circuit pattern to completely satisfy the above design conditions of an actual LSI.
Therefore, according to the automatic logic design system based on the "hardware description language", after an actual entire circuit is obtained or determined, the operator or designer must carefully review the resultant entire circuit, determine the circuit element layout in order to satisfy the above conditions, and optimally rearrange the element layout based on his determination. However, when partial modification of the element layout is to be performed after the entire circuit is completed, the effect of the modification on the surrounding circuit pattern portion must also be considered, resulting in a complex, time-consuming operation.
For example, in an logic LSI such as a microprocessor, an arithmetic and logic unit (to be referred to as an "ALU" hereinafter) of the logic LSI must be placed in the vicinity of a decoder unit for generating control signals for the ALU. This layout condition aims at minimization of the signal delay between the decoder unit and the ALU, thereby maximizing the speed of the LSI logic operation. Also, when several stages of registers are constituted, they must be placed as close as possible to shorten the wirings. When the entire circuit is to be rearranged to satisfy these conditions, no extra space must remain in the rearranged circuit pattern.
As described above, according to the automatic logic design scheme based on the "hardware description language", the operator or designer does not know at all the layout of circuit at the initial stage of a design for describing a desired function of the logic circuits with the hardware description language. Therefore, at this point of time, circuit modification/designation for optimizing the layout to satisfy the design conditions of an actual LSI cannot be performed at all. According to a "blocking design scheme", a group of logic elements that must be placed close to each other is usually treated as a single "circuit block" after the wiring is completed. However, such block assignment is impossible in the design processing using the automatic logic design system described above. As a result, the operator or designer cannot effectively utilize the advantages of the design scheme.